ChatGPT SearchOct 1, 2026

Absolutely. The key idea is that a custom AI accelerator is not just a chip-design project. It is a coordinated model → architecture → silicon → compiler/runtime → system → manufacturing project. The most successful teams co-design all of those layers rather than designing hardware first and figuring out software later.

A useful mental model is:

AI workload → numerical requirements → accelerator architecture → RTL → physical silicon → compiler/runtime → deployed system → measured workload → next revision

Here is the full process.

1. Start with the AI workload, not the chip

Suppose you're building an accelerator specifically for:

transformer inference
recommendation models
computer vision
speech recognition
diffusion
graph neural networks
a particular internal AI model

First characterize the workload.

You want to know:

Compute

What operations dominate?

For example:

math

Y = XW

may mean enormous numbers of multiply-accumulate operations:

math

MAC = A \times B + C

For a transformer, you might find that the dominant operations are:

matrix multiplication
attention
softmax
normalization
activation functions
KV-cache operations
data movement

Precision

Determine whether you actually need:

FP32
BF16
FP16
FP8
INT8
INT4
binary/ternary arithmetic

Lower precision can dramatically reduce area, energy and memory bandwidth, but potentially affects model accuracy.

Memory behavior

Often the limiting factor isn't arithmetic.

It is moving data.

You therefore measure:

model size
activation size
weight reuse
cache reuse
external DRAM bandwidth
on-chip SRAM requirements
intermediate tensor traffic

Performance target

Instead of saying "make it fast," define something like:

50,000 tokens/sec at ≤100 ms p99 latency and ≤500 W.

Or for an edge device:

30 FPS object detection at <5 W.

Those constraints fundamentally determine the architecture.

2. Establish the economic case

Before designing transistors, determine whether an ASIC is justified.

You compare:

Custom ASIC

vs.

GPU

vs.

FPGA

vs.

existing AI accelerator

The ASIC has huge non-recurring engineering costs.

A simplified model is:

math

TCO = NRE + N_{chips} \times C_{chip}

where NRE includes:

architecture
RTL development
verification
EDA
IP
masks
prototypes
engineering personnel
bring-up
software

The ASIC starts making economic sense when sufficiently high volume, performance, power savings, or strategic value amortizes that investment.

This is one reason custom accelerators are particularly attractive for hyperscalers: the same silicon may be deployed at enormous scale.

3. Write the architecture specification

Now turn the workload into a hardware specification.

You define things such as:

Compute array

For example:

             Weight Memory
                  |
                  v
        +---------------------+
        |  Matrix Multiply    |
        |                     |
Input ->| PE PE PE PE PE PE   |-> Output
        | PE PE PE PE PE PE   |
        | PE PE PE PE PE PE   |
        +---------------------+
                  |
                  v
              SRAM/cache

You might choose a:

systolic array
SIMD engine
vector processor
tensor processor
spatial dataflow architecture
reconfigurable array
combination of these

Processing elements

Each PE could contain:

multiplier
     |
     v
adder ---> accumulator

Thousands of PEs may operate simultaneously.

Memory hierarchy

You decide how much data lives in:

Registers
   ↓
Local SRAM
   ↓
Shared SRAM
   ↓
HBM / DRAM

The crucial optimization is reuse.

If a weight can be reused 100 times while sitting in SRAM rather than fetched from DRAM 100 times, the energy savings can be enormous.

4. Design the numerical architecture

This is particularly important for AI.

Imagine an accelerator supporting:

FP16
BF16
FP8
INT8
INT4

You need to determine:

accumulator precision
rounding
saturation
scaling
zero points
stochastic/deterministic behavior
conversion between formats

For example:

INT4 weights
      ↓
INT8 activation
      ↓
INT32 accumulation
      ↓
scale
      ↓
INT8 output

The hardware isn't useful if the model loses too much accuracy.

So teams perform hardware-aware model evaluation before committing to the silicon.

5. Build a software simulator

Before RTL exists, you create an architectural simulator.

It might model:

cycle counts
memory traffic
cache behavior
utilization
bandwidth
latency
power estimates

You can test architectural alternatives:

Architecture A
256 × 256 MAC array
4 MB SRAM
400 GB/s memory

vs.

Architecture B
128 × 512 MAC array
8 MB SRAM
600 GB/s memory

Then run actual representative AI models.

This phase can save enormous amounts of money because changing an architecture after tape-out is extraordinarily expensive.

6. Design the complete chip

The AI compute engine is only one part of the ASIC.

A realistic accelerator might look like:

+----------------------------------------------------+
|                    AI ASIC                         |
|                                                    |
| +----------+   +-------------------------------+   |
| | CPU/MCU  |   |       AI Compute Array        |   |
| +----------+   |                               |   |
|                |  Tensor / Vector / Scalar     |   |
|                +-------------------------------+   |
|                                                    |
| +---------+ +---------+ +-----------------------+  |
| | SRAM    | | SRAM    | | Network / DMA         |  |
| +---------+ +---------+ +-----------------------+  |
|                                                    |
| +-----------------------------------------------+  |
| | HBM / DDR / PCIe / CXL interfaces             |  |
| +-----------------------------------------------+  |
|                                                    |
| +-------------+ +----------+ +----------------+   |
| | Security    | | Debug    | | Power Mgmt     |   |
| +-------------+ +----------+ +----------------+   |
+----------------------------------------------------+

You also need:

clock generation
reset
power domains
thermal monitoring
interrupts
DMA
memory controllers
PCIe/CXL or other interfaces
security
debug
manufacturing test circuitry

7. Decide whether you need chiplets

Modern accelerators don't necessarily have to be one monolithic die.

You might instead create:

        +---------+
        | Compute |
        | Chiplet |
        +---------+
             |
       high-speed fabric
             |
+---------+  |  +---------+
| Memory  |--+--| I/O     |
| Chiplet |     | Chiplet |
+---------+     +---------+

Chiplets can allow different functions to use different process technologies and potentially improve yield or scalability.

But now you're designing:

die-to-die interfaces
package routing
power delivery
thermal interactions
multi-die verification

So packaging becomes part of the architecture.

8. Write the RTL

Now the architecture becomes actual digital hardware.

RTL—typically SystemVerilog—is used to describe the behavior of the hardware.

Conceptually:

input tensors
     ↓
DMA
     ↓
SRAM
     ↓
scheduler
     ↓
compute array
     ↓
accumulator
     ↓
post-processing
     ↓
output

Engineers implement:

datapaths
state machines
schedulers
interconnects
caches
memory controllers
register interfaces
error handling
configuration logic

This is where the abstract architecture becomes an actual circuit design.

9. Verification becomes enormous

You don't simply simulate the chip once.

You need to demonstrate that it behaves correctly across an enormous number of situations.

Typical techniques include:

Simulation

Run RTL against expected results.

Formal verification

Mathematically prove properties of portions of the design.

Assertions

For example:

if request_valid == 1
then request eventually receives response

Randomized testing

Generate huge numbers of unusual sequences.

Coverage

Measure which:

lines
branches
states
functional scenarios

have actually been exercised.

Synopsys describes coverage closure, simulation, formal verification and related validation as core parts of ASIC development.

10. Create the software stack in parallel

This is one of the most important parts.

A custom accelerator is effectively useless if developers can't run models on it.

The stack often looks like:

PyTorch / TensorFlow
          ↓
       Model IR
          ↓
       Graph compiler
          ↓
   Hardware-specific
      optimization
          ↓
      Code generation
          ↓
     Runtime/driver
          ↓
        ASIC

A compiler might:

identify operators
fuse operations
quantize tensors
schedule computation
allocate SRAM
tile matrices
generate accelerator instructions
schedule DMA
synchronize compute units

This is conceptually similar to how NVIDIA TensorRT turns a model into an optimized hardware-specific inference engine. TensorRT's documented flow includes model parsing, optimization, engine generation and runtime execution.

For your ASIC, however, you're building the equivalent hardware/compiler ecosystem yourself.

11. Synthesis

The RTL is then transformed into a gate-level representation.

Conceptually:

SystemVerilog RTL
       ↓
logic synthesis
       ↓
standard cells
       ↓
gate-level netlist

The synthesis tools map your logical design into actual cells available in the selected semiconductor process.

For example:

AND
OR
MUX
flip-flop
buffer
adder
etc.

At this stage you're increasingly dealing with real:

area
timing
power

rather than just logical functionality.

12. Physical design

Now the question becomes:

Where do billions of transistors and their interconnections physically go?

The flow includes:

Floorplanning

Decide where major blocks live.

+--------------------------------+
| SRAM       | Compute Array     |
|            |                  |
|------------|                  |
| Compute    | Compute          |
|            |                  |
|------------|------------------|
| IO         | Memory Interface |
+--------------------------------+

Placement

Place individual cells.

Clock-tree synthesis

Distribute clock signals with controlled skew.

Routing

Connect everything using metal layers.

Optimization

Continuously optimize:

performance
power
area
congestion

Synopsys describes synthesis, floorplanning, placement and routing as the implementation stage where PPA and congestion are optimized.

13. Signoff

Before fabrication, the design goes through increasingly stringent checks.

Examples:

Timing

Does every path meet its timing requirement?

Power

Does it exceed power limits?

Physical verification

Does the layout obey the fabrication rules?

DRC

Design Rule Check

Does the layout conform to the foundry's manufacturing rules?

LVS

Layout Versus Schematic

Does the physical implementation correspond to the intended circuit?

Signal integrity

Could neighboring wires interfere with one another?

IR drop

Does resistance in the power network cause unacceptable voltage loss?

Electromigration

Can metal reliably carry the current over the chip's lifetime?

DFT

Design-for-test structures are inserted so manufactured chips can be tested.

Common DFT structures include:

scan chains
memory BIST
logic BIST
test compression

Synopsys specifically identifies scan, BIST, simulation, static timing and formal verification as important pre-tapeout validation activities.

14. Tape-out

Eventually you reach:

Tape-out

The final physical design database is delivered to the foundry.

Historically this involved GDSII; modern flows can involve related physical-design database formats as well.

The fundamental idea is:

logical design
      ↓
verified physical layout
      ↓
manufacturing database
      ↓
FOUNDry

At this point, you've crossed an important boundary:

software can still be changed; transistors generally cannot.

15. Wafer fabrication

The foundry turns the design into physical silicon.

Very simplified:

silicon wafer
     ↓
deposition
     ↓
photoresist
     ↓
lithography
     ↓
etch
     ↓
implantation
     ↓
cleaning
     ↓
repeated many times
     ↓
transistors + metal layers

Modern processes involve an enormous number of tightly controlled fabrication steps.

The result is a wafer containing many copies of the die.

16. Wafer testing

Before cutting the wafer apart, manufacturers test the dies.

This is where the DFT infrastructure becomes important.

Tests may identify:

dead dies
timing failures
memory defects
stuck-at faults
interface problems
power problems

You calculate the yield:

math

Yield = \frac{\text{Good dies}}{\text{Total dies}}

Yield is enormously important economically.

A theoretically fantastic chip that produces too few good dies may be commercially unusable.

17. Packaging

The good dies are separated and packaged.

For a high-performance AI accelerator, packaging may be extremely sophisticated.

For example:

       HBM
    +-------+
    | Memory|
    +-------+
        |
+----------------+
| AI Accelerator |
|      Die       |
+----------------+
        |
     substrate
        |
      PCB

The package has to solve:

power delivery
high-speed signaling
thermal dissipation
mechanical reliability
memory bandwidth

For advanced accelerators, packaging can therefore be almost as strategically important as the transistor design.

18. Post-silicon bring-up

Now you finally receive physical chips.

The first silicon is commonly called:

engineering samples

You put one on a test board and essentially ask:

Does this thing actually work?

Engineers bring up:

clocks
reset
memory
PCIe/CXL
firmware
security
compute units
DMA
interrupts

Then they start running progressively larger workloads.

19. Silicon validation

Now compare the real chip against your predictions.

You measure:

TOPS
latency
throughput
bandwidth
utilization
power
temperature
reliability

You might discover something like:

Simulation:
95% compute utilization

Silicon:
62%

Then you investigate.

Perhaps the compiler is scheduling poorly.

Perhaps SRAM bandwidth is insufficient.

Perhaps the network between compute blocks is congested.

Perhaps the model has unexpected memory behavior.

This is why hardware/software co-design is so important.

20. Optimize the compiler against real silicon

This is where things get interesting.

Suppose the hardware has:

256 × 256 MAC array

but your compiler only achieves 40% utilization.

You can potentially change the compiler rather than the silicon.

For example:

Model graph
    ↓
operator fusion
    ↓
tiling
    ↓
memory scheduling
    ↓
DMA scheduling
    ↓
instruction generation
    ↓
ASIC

You tune those decisions using real performance measurements.

This is similar in principle to TensorRT's optimization approach: its builder selects optimized implementations for layers on a target device, rather than simply executing a generic model.

21. Production ramp

Once the chip is validated:

Engineering samples
       ↓
qualification
       ↓
production release
       ↓
volume wafer production
       ↓
packaging
       ↓
system assembly
       ↓
data-center / edge deployment

You establish:

manufacturing test limits
binning
reliability screening
thermal limits
firmware versions
production diagnostics
supply chain

22. Then the real optimization begins

Once thousands or millions of chips are deployed, you collect real-world data.

You discover:

which models dominate
where power is spent
which operators are bottlenecks
which memory patterns hurt
what temperatures occur
which compiler optimizations matter

That feeds directly into the next generation.

So the actual development loop becomes:

      ┌───────────────────────────────┐
      │                               │
      ▼                               │
AI workloads → architecture → silicon │
      ↑                         ↓      │
      │                    measurements│
      │                         ↓      │
models ← compiler ← software ← silicon │
      │                               │
      └───────────────────────────────┘

The entire process in one view

Here is the simplified end-to-end pipeline:

1. Choose AI workload
          ↓
2. Profile models
          ↓
3. Define performance/power/cost targets
          ↓
4. Design accelerator architecture
          ↓
5. Build architectural simulator
          ↓
6. Co-design numerical formats
          ↓
7. Design memory hierarchy/interconnect
          ↓
8. Design complete SoC/chiplet system
          ↓
9. Develop compiler + runtime
          ↓
10. Write RTL
          ↓
11. Functional verification
          ↓
12. Synthesis
          ↓
13. Physical design
          ↓
14. Timing/power/physical signoff
          ↓
15. DFT insertion + test development
          ↓
16. TAPE-OUT
          ↓
17. Wafer fabrication
          ↓
18. Wafer test
          ↓
19. Packaging
          ↓
20. Package test
          ↓
21. Silicon bring-up
          ↓
22. Silicon validation
          ↓
23. Compiler/model optimization
          ↓
24. Production ramp
          ↓
25. Field deployment
          ↓
26. Next-generation architecture

A concrete example: building a transformer-inference ASIC

Imagine your objective is:

Very high-throughput, low-power LLM inference.

You might discover that the workload heavily stresses:

1. Matrix multiplication

So you create a large tensor/MAC array.

2. Memory bandwidth

So you add large on-chip SRAM and perhaps HBM.

3. KV cache

So you create specialized memory-management mechanisms.

4. Quantization

You support INT8/INT4/FP8 datapaths.

5. Attention

You add specialized hardware for attention-related operations.

6. Scheduling

You create a compiler that tiles tensors to keep the compute array busy.

7. Model evolution

You make the accelerator programmable enough that a new transformer architecture doesn't immediately make the ASIC obsolete.

This last point is crucial.

A truly specialized ASIC isn't necessarily one that implements only one neural network. Often the sweet spot is:

fixed-function hardware around a programmable computational core

That gives you much of the efficiency of specialization without completely sacrificing flexibility.

Where the difficulty actually lies

People often imagine:

"Build a giant matrix multiplier."

That's actually only one piece.

The hard parts are frequently:

Layer	Core problem
Model	What computation actually matters?
Algorithm	What precision can we use?
Architecture	How do we exploit parallelism?
Memory	How do we avoid moving data?
Interconnect	How do compute units communicate?
RTL	How do we implement it correctly?

And modern chip development is increasingly computationally intensive itself; EDA vendors describe RTL simulation, implementation, circuit simulation, physical verification, library characterization and signoff as major compute workloads.

The three disciplines you ultimately have to combine

If you wanted to become capable of actually creating one, I'd divide the knowledge into three major tracks:

1. Computer architecture

Learn:

digital logic
computer architecture
parallel processors
caches/SRAM
memory systems
interconnects
SIMD/vector architectures
systolic arrays
accelerators
performance modeling

2. Semiconductor engineering

Learn:

CMOS
VLSI
RTL/SystemVerilog
synthesis
STA
floorplanning
placement/routing
DFT
physical verification
semiconductor fabrication
packaging

3. AI/compiler engineering

Learn:

neural-network architectures
quantization
model graphs
MLIR/LLVM-style compiler infrastructure
operator fusion
tiling
scheduling
memory planning
kernel generation
runtime/driver design

The intersection of those three is where custom AI silicon becomes particularly powerful.

For comparison, NVIDIA's current software stack illustrates why the hardware alone isn't the product: its inference stack spans model optimization, compilation, runtime, quantization and deployment, with different layers targeting different hardware and workloads.

One important practical distinction

There are really three different projects people call "building an AI accelerator":

Level 1 — FPGA accelerator:
You design hardware logic and deploy it on an existing FPGA. Great for learning and prototyping.

Level 2 — ASIC accelerator:
You design RTL, use an EDA flow, tape out through a foundry, and receive physical silicon.

Level 3 — Production AI accelerator company:
Everything above plus compiler, runtime, firmware, board, package, memory, manufacturing, supply chain, model support and customers.

Level 3 is where the enormous complexity—and potentially the enormous leverage—comes from.

If your goal is to understand how you could personally go from Python/PyTorch model → RTL → FPGA prototype → eventually a real manufactured AI ASIC, I can also lay out a practical 0-to-silicon learning/build roadmap, including the open-source tools and a realistic first accelerator you could build.

Sources cited in this answer4

Requirement

Recommended starting point

Turnkey, disconnected sovereign cloud

Google Distributed Cloud air-gapped

Customer-owned, customizable GPU cloud

HPE, Dell or Supermicro + NVIDIA

Large-scale model training

NVIDIA HGX B200/B300-class systems

Distributed inference and smaller secure nodes

NVIDIA RTX PRO Server-class systems

Vendor

What to investigate

Official link

Expedera

Origin AI inference IP

expedera.com

Quadric

Chimera general-purpose NPU (GPNPU)

.io

Your design target

Vendors to evaluate first

Low-power edge inference

Arm, CEVA, Andes

Generative AI and transformer inference

CEVA, Cadence, Arm, Imagination

Computer vision and embedded SoCs

VeriSilicon, Cadence, Andes

Programmable AI compute alongside graphics

Imagination,

Vendor

Relevant silicon

Why evaluate it for drones

Qualcomm

QRB5165 / Flight RB5

Particularly relevant to drones: heterogeneous CPU/GPU/DSP/NPU, ISP, camera support and connectivity in one platform. Qualcomm specifies 15 TOPS AI, with the Hexagon Tensor Accelerator providing 8 TOPS, and supports up to seven concurrent cameras.

Hailo

Hailo-8 / Hailo-8L / Hailo-10H

Strong candidate when you already have a host processor and want a dedicated low-power vision accelerator. Hailo-8 provides 26 TOPS at typically 2.5 W, with integrated memory and M.2/PCIe options; Hailo-8L provides 13 TOPS.

Renesas

RZ/V2N, RZ/V series

Very relevant for embedded vision: the RZ/V2N combines four Cortex-A55 cores, ISP options, camera interfaces and Renesas' DRP-AI3 accelerator at up to 15 TOPS.

Texas Instruments

TDA4VM / TDA4VM-Q1

Excellent candidate if sensor processing, deterministic real-time processing and safety matter. It combines an 8-TOPS deep-learning accelerator, vision accelerators, ISP, DSPs, Cortex-A72/R5F cores and extensive camera/PCIe connectivity. TI explicitly targets robotics and machine vision.

Ambarella

CV3-AD family / CVflow

Worth investigating for an image-heavy autonomy stack. Its CV3 family combines a neural vector processor with dedicated processing for classical computer vision, radar and multi-sensor perception.

NXP

i.MX 95 + eIQ Neutron NPU

Interesting if you want a Linux embedded platform with security, safety and heterogeneous edge compute. NXP positions i.MX 95 for aerospace, automotive and industrial edge applications with AI-accelerated vision.

Axelera AI

Metis AIPU / Embedded 110M

A compelling discrete accelerator to benchmark when inference throughput per watt dominates. Metis claims up to 214 TOPS INT8 and 15 TOPS/W, with a sub-10-W AIPU architecture and Voyager SDK.

MediaTek

Genio 1200

More of a general embedded/IoT SoC option, but its 6-nm Genio 1200 integrates a 4.8-TOPS NPU, dual ISPs, three 4-lane CSI interfaces and industrial-temperature support.

Synaptics

Astra SL1640

Worth a lower-power comparison point: quad Cortex-A55, 1.6+ TOPS NPU, GPU, video pipelines and Linux/Android support.

Arm

Ethos-U55/U85 IP

Different procurement model: if you're designing your own ASIC/SoC, evaluate Arm's configurable NPU IP rather than buying an accelerator chip. Ethos-U55 targets extremely constrained embedded systems and emphasizes low area and energy consumption.

#	Brand	Recommended for	Mentioned in
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30	NVIDIA Inference (NVIDIA Inference Stack)NVIDIA product line 10%		10%
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37	VeriSilicon 10%		10%
38	Quadric 10%		10%
39	SnapdragonQualcomm product line 9%		9%
40	Google Distributed CloudAlphabet product line 9%		9%
41	Cerebras Systems 9%		9%
42	Groq 9%		9%
43	Tenstorrent 8%		8%
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59	Xylo 5%		5%
60	Alchip Technologies 5%		5%
61	Google StoreOwned by Alphabet 5%		5%
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76	Arm Ethos-U55Arm product line 4%		4%
77	Microsoft AzureMicrosoft product line 4%		4%
78	i.MX 9NXP Semiconductors product line 4%		4%
79	Rockchip 4%		4%
80	Meta AI 4%		4%
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82	Ambiq 3%		3%
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90	Global AI 2%		2%
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92	Mirantis 2%		2%
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94	Google CoralAlphabet product line 2%		2%
95	MemryX 2%		2%
96	Etched 2%		2%
97	NVIDIA H100NVIDIA product line 2%		2%
98	NVIDIA DGXNVIDIA product line 2%		2%
99	Infineon Technologies 2%		2%
100	NXP i.MXNXP Semiconductors product line 2%		2%

Brand	ChatGPT Search	Google AI Mode
Qualcomm	48%	38%
Intel	40%	39%
NVIDIA	41%	37%
Hailo	36%	35%
AMD	35%	26%
NXP Semiconductors	32%	29%
Apple	26%	28%
MediaTek	34%	17%
Ambarella	30%	13%
Arm	23%	19%

Company	AI silicon	Primary market
Google	TPU	Cloud AI training and inference
Amazon / AWS	Trainium, Inferentia	Cloud AI training and inference
Microsoft	Maia	Azure AI infrastructure
Meta	MTIA	Recommendation and AI inference
Apple	Neural Engine	On-device AI
Qualcomm	Hexagon NPU	Mobile, PC and automotive
MediaTek	Integrated AI accelerators	Mobile and edge devices
Tenstorrent	AI accelerators and RISC-V IP	AI compute and custom silicon

Company	Relevant technology	Best-fit applications
Apple	Neural Engine in Apple Silicon	On-device AI in iPhones, iPads and Macs; models run through Core ML.
MediaTek	Integrated AI processing in mobile SoCs	Smartphones, connected devices and consumer electronics
Google	Tensor mobile SoCs and Edge TPU products	Mobile AI and embedded inference
Texas Instruments	Embedded processors with AI capabilities	Industrial sensing, motor control and edge vision
DEEPX	Dedicated low-power AI accelerators	Embedded vision, robotics and autonomous devices
Kneron	Edge AI SoCs and NPUs	Smart cameras, access control and IoT

Most-mentioned brands

Latest insights

Recommendations by AI engine

Questions by topic4

1. Companies that design custom AI silicon

Sources AI cites99

See where your brand stands in this ranking

See where your brand stands in this ranking

Questions by topic4

1. Companies that design custom AI silicon

2. Companies that develop NPU and AI processor IP

3. Companies designing their own AI accelerators

4. Which companies should you evaluate first?

To refine your shortlist

Sources cited in this answer13

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Sources cited in this answer4

1. Start with the AI workload, not the chip

Compute

Precision

Memory behavior

Performance target

2. Establish the economic case

3. Write the architecture specification

Compute array

Processing elements

Memory hierarchy

4. Design the numerical architecture

5. Build a software simulator

6. Design the complete chip

7. Decide whether you need chiplets

8. Write the RTL

9. Verification becomes enormous

Simulation

Formal verification

Assertions

Randomized testing

Coverage

10. Create the software stack in parallel

11. Synthesis

12. Physical design

Floorplanning

Placement

Clock-tree synthesis

Routing

Optimization

13. Signoff

Timing

Power

Physical verification

DRC

LVS

Signal integrity

IR drop

Electromigration

DFT

14. Tape-out

15. Wafer fabrication

16. Wafer testing

17. Packaging

18. Post-silicon bring-up

19. Silicon validation

20. Optimize the compiler against real silicon

21. Production ramp

22. Then the real optimization begins

The entire process in one view

A concrete example: building a transformer-inference ASIC

Where the difficulty actually lies

The three disciplines you ultimately have to combine

1. Computer architecture

2. Semiconductor engineering

3. AI/compiler engineering

One important practical distinction

Sources cited in this answer4

Sources cited in this answer1

Leading companies offering edge AI chips

1. The Heavyweight Leader: NVIDIA (Jetson Orin Series)

Providers to shortlist

Which architecture should you choose?

What to verify before issuing an RFP