We are designing an AI hardware accelerator. Who offers IP cores for neural processing units (NPU)?

If you are designing an AI hardware accelerator or System-on-Chip (SoC) and looking to license pre-verified Neural Processing Unit (NPU) silicon intellectual property (IP) rather than building an inference engine from scratch, several major semiconductor IP vendors offer scalable, production-proven RTL solutions complete with software toolchains.

1. Major Commercial NPU IP Providers

• Arm (Ethos Series): Arm provides the Arm Ethos NPU family, which ranges from ultra-low power micro-NPUs for Cortex-M microcontrollers (Ethos-U55/U65) up to higher-performance units for mobile and edge applications (Ethos-N series). They integrate tightly with Arm CPUs and use unified software stacks like the Arm Compute Library.
• Cadence (Neo NPU): Cadence offers the Cadence Neo NPU IP platform, which is highly configurable (scaling from sub-TOPS to over 100 TOPS) and tailored for edge, automotive, IoT, and generative AI workloads (including transformers and small/large language models). It is paired with the NeuroWeave SDK.
• CEVA (NeuPro / NeuPro-M): CEVA specializes in wireless, smart-sensing, and edge AI IP. Their Ceva-NeuPro-M NPU architecture is engineered specifically for deep learning, computer vision, and generative AI/transformers at the edge, offering high token-per-second-per-watt efficiency.
• Imagination Technologies (IMG Series / Neural Cores): Best known for graphics, Imagination provides Imagination Edge AI & Compute IP that scales classic GPU pipelines into dense Neural Cores or multi-core Neural Network Accelerators (NNAs) reaching hundreds of TOPS, heavily targeting automotive (ADAS) and high-throughput edge nodes.
• VeriSilicon (Vivante VIP / VIPNano Series): VeriSilicon provides highly scalable VeriSilicon NPU IP solutions deployed widely across smart homes, surveillance, automotive, and edge servers. Their VIP9000 series supports both CNNs and Transformer models and comes with the Acuity software toolkit.

2. Alternative & Open-Standard Approaches (RISC-V / FPGA)

• Andes Technology & SiFive: If you are building a custom RISC-V-based accelerator, companies like Andes provide vector processing units (VPUs) and custom extension frameworks (such as their AndesCore with vector extensions) well-suited for handling heavy parallel matrix math and machine learning workloads.
• FPGA Vendors (e.g., Lattice Semiconductor): If your target implementation involves FPGAs rather than an ASIC tape-out, vendors like Lattice offer dedicated embedded solutions like the Lattice CNN Plus Accelerator IP Core , which maps natively onto low-power programmable logic.

To help narrow down the best IP option, could you share:

• What is your target application or market (e.g., ultra-low-power IoT, automotive ADAS, or high-throughput edge server)?
• What is your intended compute scale (TOPS) and target process node?

Several established vendors license NPU/AI-accelerator IP cores:

• Arm — Ethos-U55/U65/U85 NPUs for embedded/edge inference.
• Cadence — Neo NPU, scalable and configurable for edge through higher-performance AI workloads.
• Synopsys — ARC NPX NPU family, including configurable AI acceleration IP.
• CEVA — NeuPro/NeuPro-Nano NPU IP targeting edge AI and TinyML.
• Imagination Technologies — AI accelerator/NNA IP.
• VeriSilicon — AI/NPU and vision-processing IP.
• Expedera — scalable NPU IP.
• Quadric — programmable AI accelerator/NPU IP.
• DMP (Digital Media Professionals) — edge-AI accelerator IP.

CEVA's latest filing specifically identifies Arm, Cadence, Cambricon, DMP, Quadric, Imagination, NVDLA, and VeriSilicon as competitors in edge NPU IP.

For an accelerator architecture, the key comparison is PPA, INT8/INT4/FP16 support, transformer/LLM capability, memory architecture, programmability, toolchain, and licensing model.

Yes. If you mean licensable semiconductor IP that you can integrate into your own SoC/ASIC/accelerator, there are several established suppliers. The most relevant ones are:

The big four I'd evaluate first

Arm — Ethos

Arm's Ethos-U family is a mature choice if your accelerator is targeting embedded/edge inference. Current offerings include Ethos-U55, U65 and U85. U85 scales from 128–2,048 MACs and up to 4 TOPS at 1 GHz, with native transformer support.

Cadence Design Systems — Neo NPU

Cadence's Neo NPU family is particularly interesting if you want configurability and a broader AI subsystem. Cadence says Neo scales from 8 GOPS to 80 TOPS per core, with multicore configurations reaching hundreds of TOPS. Its NeuroWeave SDK provides a common software flow across its AI IP.

Synopsys — ARC NPX

Synopsys' ARC NPX6 is one of the more capable licensable NPU architectures if you're designing a substantial accelerator rather than a tiny MCU NPU. It scales from 1K to 96K MACs, supports CNNs, RNNs/LSTMs, transformers and GenAI, and can be configured into multicore clusters. Synopsys currently quotes up to 250 TOPS per NPU and 3,500 TOPS for an 8-NPU cluster with sparsity.

CEVA — NeuPro-M

CEVA's NeuPro-M is worth looking at if your roadmap includes transformers and generative AI. It is explicitly positioned as a scalable NPU IP family for edge and cloud inference and models with more than a billion parameters.

One important distinction

If you are designing an AI hardware accelerator, I'd separate vendors into three categories:

1. Complete licensable NPU architectures — Arm Ethos, Cadence Neo, Synopsys ARC NPX, CEVA NeuPro.
2. AI accelerator building blocks / configurable DSPs — useful if you want to develop your own architecture around MAC/tensor/vector engines.
3. Full custom accelerator design — you license lower-level IP (NoC, SRAM, HBM/DDR controllers, PCIe, etc.) and build the NPU architecture yourself.

The right choice depends heavily on whether you're building an edge inference chip, automotive accelerator, datacenter inference ASIC, or a standalone AI accelerator, and on your target INT8/INT4/FP16/BF16, TOPS, memory bandwidth, sparsity and software-stack requirements.

One caveat on the corporate landscape: Synopsys announced that GlobalFoundries acquired its Processor Solutions business on June 1, 2026, so if you're evaluating ARC NPX specifically, I'd verify the current licensing/ownership arrangement during procurement.

If you tell me your target (e.g. “10–100 TOPS, INT8/FP16, PCIe-attached accelerator”), I can make a vendor-by-vendor comparison of NPU architecture, MAC array, supported precisions, memory architecture, compiler/SDK, PPA, and licensing model.

Cadence Design Systems — Neo NPU

Cadence's Neo NPU family is particularly interesting if you want configurability and a broader AI subsystem. Cadence says Neo scales from 8 GOPS to 80 TOPS per core, with multicore configurations reaching hundreds of TOPS. Its NeuroWeave SDK provides a common software flow across its AI IP.

Synopsys — ARC NPX

Synopsys' ARC NPX6 is one of the more capable licensable NPU architectures if you're designing a substantial accelerator rather than a tiny MCU NPU. It scales from 1K to 96K MACs, supports CNNs, RNNs/LSTMs, transformers and GenAI, and can be configured into multicore clusters. Synopsys currently quotes up to 250 TOPS per NPU and 3,500 TOPS for an 8-NPU cluster with sparsity.

CEVA — NeuPro-M

CEVA's NeuPro-M is worth looking at if your roadmap includes transformers and generative AI. It is explicitly positioned as a scalable NPU IP family for edge and cloud inference and models with more than a billion parameters.

Designing an AI hardware accelerator means choosing whether to build your neural processing engine from scratch or license proven semiconductor IP. Several tier-one and specialized IP vendors offer licensable Neural Processing Unit (NPU) cores mapped for distinct power, area, and performance (PPA) targets.

Major NPU IP Core Providers

• Arm (Ethos Series): Arm provides the Arm Ethos NPU architecture (such as the Ethos-U55, U65, and high-performance U85), optimized to scale from microcontrollers up to deep edge infrastructure. They integrate tightly with Cortex-A and Cortex-M ecosystems, supported by the Vela compiler for quantized networks.
• Cadence (Neo / Tensilica Series): Cadence offers scalable Cadence Neo NPUs and Tensilica DSP/AI IP that scale from single-digit GOPS up to 80+ TOPS in a single core. Their common NeuroWeave software development kit addresses edge, IoT, vision, and automotive applications.
• Synopsys (ARC Series): Synopsys licenses ARC-V and ARC processor/NPU IP paired with the MetaWare software toolchain. Their solutions target embedded vision, automotive, and consumer edge AI devices requiring tight host-processor offloading.
• Imagination Technologies (Series3NX): Imagination offers flexible NPU configurations aimed at high-efficiency machine vision and automotive workloads. They provide distinct commercial terms, including programs like Open Access for evaluating silicon-proven core layouts.
• BrainChip (Akida): BrainChip specializes in neuromorphic BrainChip Akida IP event-based processing, offering an ultra-low-power event-driven architecture designed for intelligent edge sensors and specialized ASIC integration.

If you want to narrow down the options , tell me:

• What is your target power envelope (e.g., sub-1W ultra-low-power edge vs. multi-tens/hundreds of TOPS)?
• What is the primary target application (IoT/microcontroller, automotive ADAS, or mobile/edge device)?

Yes. There is a fairly mature market for licensable NPU/neural-accelerator IP, ranging from tiny embedded NPUs to multi-hundred-TOPS accelerators for edge/automotive/AI SoCs.

Major NPU IP vendors

How I'd narrow the field

For a new commercial AI accelerator, I'd put these four at the top of the initial evaluation:

1. CEVA NeuPro-M — particularly attractive for a new design where transformer/GenAI support and a complete software stack matter. CEVA reported 10 NeuPro NPU licensing agreements in 2025, so it has demonstrated active licensing traction.
2. Cadence Neo / Tensilica DNA — strong choice if you want a mixture of dedicated neural acceleration and programmability.
3. Arm Ethos-U85 — compelling if you're building an Arm-based embedded/edge SoC and want the lowest ecosystem/integration risk.
4. Synopsys ARC NPX6 / now GF — worth evaluating for substantially larger accelerator configurations. Be careful with the June 2026 Synopsys→GlobalFoundries transaction when determining who will actually license/support the IP.

VeriSilicon is also worth including if your SoC needs a broader collection of multimedia/vision IP, while BrainChip is more of a specialized choice for neuromorphic/event-driven workloads.

One important distinction: "NPU IP" isn't necessarily interchangeable with a complete AI accelerator. When evaluating vendors, I'd compare not just TOPS, but supported precisions (INT4/INT8/FP16/etc.), sparsity, SRAM architecture, memory bandwidth, transformer operators, programmability, compiler quality, ONNX/TVM support, safety certifications, process-node PPA, and licensing/royalty structure.

If you tell me your target—e.g. automotive, edge inference, datacenter, smartphone, or custom GenAI ASIC, plus approximate TOPS and process node—I can make a much more useful vendor-by-vendor NPU IP comparison, including architecture, MAC count, precision, software stack, PPA, licensing model, and likely competitors.

When designing an AI hardware accelerator or integrating an NPU into a custom System-on-Chip (SoC), the Neural Processing Unit (NPU) IP landscape spans major EDA/IP conglomerates, specialized signal-processing licensors, and dedicated ultra-low-power or high-performance NPU startups.

The primary providers of licensable NPU IP cores are categorized below by their ecosystem and focus:

1. Major EDA & General-Purpose IP Giants

• Arm: Offers the Arm Ethos NPU series (such as Ethos-U for microcontrollers/edge and Ethos-N for mainstream mobile/consumer devices). They are deeply integrated with Arm Cortex CPUs and the Arm NN software development stack.
• Cadence: Provides the Tensilica Xtensa and NeoNPU architectures, which are highly configurable and target audio, vision, and high-performance edge/mobile LLM inference with robust software toolchains.
• Synopsys: Offers the DesignWare ARC EV (Embedded Vision) and ARC NPX processor IP lines, featuring tightly integrated vector DSP and neural processing capabilities optimized for automotive, IoT, and surveillance.

2. Specialized & Wireless/Audio/Vision IP Licensors

• CEVA: Known for its NeuPro and NeuPro-M NPU family. CEVA specializes in multi-sensor AI workloads spanning automotive, industrial, consumer, and PC edge infrastructure, balancing scalar, vector, and neural matrix processing.
• Imagination Technologies: Offers the Imagination Series architecture, focusing on high-efficiency compute and neural network acceleration for automotive and mobile environments.
• VeriSilicon: Provides a scalable VIP (Vivante Intelligence Processor) NPU IP core lineup that is widely adopted across automotive ADAS, smart surveillance, and wearables.

3. Dedicated & Boutique NPU / Edge AI IP Startups

• Quadric: Licenses Chimera GPNPU (General Purpose NPU), which merges traditional DSP processing with machine learning matrix acceleration into a single core running one unified software toolchain.
• Expedera: Specializes in highly customizable, high-performance, and low-latency neural network accelerator IP optimized for edge inference from mobile to automotive.
• OPENEDGES Technology: Combines NPU IP (ENLIGHT ) with advanced memory controller and interconnect IP, giving a unified approach to memory bandwidth bottlenecks in AI chips.
• Other niche players: Companies like EdgeCortix, BrainChip (neuromorphic IP), and Andes Technology (RISC-V vector/NPU extensions) also provide alternative licensing models depending on whether you lean toward standard ISA extensions or dedicated dataflow engines.

If you can share your target power envelope (e.g., ultra-low-power IoT vs. datacenter/edge server) and intended workloads (e.g., computer vision vs. generative AI/LLMs) , I can help narrow down which of these IP vendors best fits your architectural constraints.

If you are designing an ASIC or SoC for an AI hardware accelerator, licensing a pre-verified Neural Processing Unit (NPU) IP core can drastically reduce your time-to-market. Several major semiconductor IP vendors offer licensable NPU architectures, ranging from ultra-low-power microcontrollers to high-performance data center and automotive accelerators.

Major NPU IP Core Providers

• Arm (Ethos Series)
  • Offerings: Ethos-U (for microcontrollers/Cortex-M edge devices, like the U55/U65) and Ethos-N (for higher-performance Cortex-A systems like smartphones and DTVs, e.g., Ethos-N78).
  • Best for: Deep integration with Arm-based SoCs, unified toolchains (Arm NN / Vela compiler), and strict power/area optimization at the edge.
• Synopsys (ARC-Based NPX / MPX Series)
  • Offerings: Synopsys ARC Processor IP and the NPX6/MPX6 NPU IP family.
  • Best for: Scalable performance from 1 TOP to thousands of TOPS. Well-suited for automotive (with ISO 26262 functional safety options), IoT, and high-end edge AI handling both transformers and CNNs.
• Cadence (Tensilica Neo / NeuroEdge)
  • Offerings: Tensilica Neo NPU architectures alongside the NeuroEdge AI Co-Processor (AICP).
  • Best for: Highly customizable DSP/AI subsystems. Cadence allows tight integration with their own or third-party NPU IP, targeting audio, vision, automotive, and edge-to-enterprise data processing.
• Imagination Technologies (Imagination Accelerator / NN)
  • Offerings: Series5NX and related neural network accelerator IP architectures.
  • Best for: Scalable multi-core designs aimed at automotive, consumer, and mobile graphics/compute convergence.
• VeriSilicon (VIP Series)
  • Offerings: Vivante VIP Nano and VIP Pro Neural Processor IP cores.
  • Best for: Highly modular, low-power embedded devices, wearables, and surveillance chips with extensive software framework support.
• Quadric (Chimera GPNPU)
  • Offerings: Chimera General-Purpose NPU (GPNPU) IP.
  • Best for: Designs requiring a fully C++ programmable core rather than fixed-function NPU blocks, combining DSP and machine learning workload capabilities into a single unified architecture.

Key Evaluation Criteria for NPU IP

1. Software Stack & Toolchain: An NPU is only as good as its compiler. Look closely at how easily the vendor's toolchain maps PyTorch/ONNX models (and handles quantization to INT8/INT4). Fragmented compilers can cause major integration bottlenecks.
2. Data Type Support: Ensure the IP natively supports the precision levels your accelerator requires (e.g., INT8/INT16 for efficient edge inference vs. FP16/BF16/FP8 support for generative AI and training workloads).
3. Memory Bandwidth & Compression: Generative AI and large language models are heavily memory-bound. Look for IP that includes built-in weight/data compression or specialized DMA architectures to limit external DRAM bottlenecks.

If you can share the target application (e.g., ultra-low-power edge, automotive safety, or high-throughput data center) and your expected performance range (TOPS) , I can help narrow down which of these NPU IP vendors best fits your architectural requirements.

Yes. If you are building an SoC/ASIC and want to license an NPU/AI-accelerator IP core rather than design the accelerator from scratch, there is a fairly broad supplier landscape.

Major NPU IP vendors

There are also more specialized players worth evaluating, including Imagination Technologies, Expedera, Quadric, Digital Media Professionals (DMP) and BrainChip. CEVA itself identifies these companies, along with Arm, Cadence, VeriSilicon and Andes, as competitors in the DSP/NPU/processor-IP market.

A few distinctions matter

For an edge/embedded SoC: I'd put Arm Ethos, Cadence Neo, CEVA NeuPro-Nano/M, VeriSilicon Vivante and Andes AnDLA near the top of the initial evaluation list.

For a large AI accelerator: CEVA NeuPro-M and the ARC NPX family are more interesting because of their scalability. ARC NPX6, for example, can scale from 1K to 96K MACs and supports multi-NPU configurations up to 3,500 TOPS with sparsity.

For RISC-V: Andes is especially relevant, although its AnDLA is more accurately described as a deep-learning accelerator IP than a complete general-purpose NPU.

For a complete vision SoC: VeriSilicon is worth particular attention because its NPU can be integrated with its ISP, GPU and video IP, potentially reducing integration work.

One important caveat for your sourcing exercise: "NPU IP" isn't a standardized product category. Some vendors license a complete programmable NPU including compiler/runtime/software, while others provide primarily an accelerator RTL block. The software stack, supported operators/data types, memory architecture, coherency interface, and ability to customize the datapath can matter more than the headline TOPS figure.

If you're actually selecting an IP for a new accelerator, I can also put together a vendor-by-vendor comparison of ~10 NPU IP cores covering TOPS, TOPS/W, INT8/INT4/FP16 support, transformer/GenAI support, sparsity, SRAM/cache architecture, RISC-V/Arm integration, licensing model, process-node availability, and known silicon deployments.

Designing an AI hardware accelerator means you don’t necessarily have to build your tensor engines or vector pipelines from scratch. Several major semiconductor IP vendors offer licensable Neural Processing Unit (NPU) and Tensor Processor IP cores that you can integrate directly into your custom System-on-Chip (SoC) or ASIC.

The primary commercial providers of licensable NPU IP cores span a range of specializations—from ultra-low-power microcontrollers to high-performance multi-core edge and data center accelerators:

1. Major Established IP Vendors

• Arm (Ethos Series): Arm offers the Ethos NPU family, which is split into distinct efficiency tiers. The Ethos-U line (like the Ethos-U65 and Ethos-U85) targets microcontrollers and embedded devices (Cortex-M and Cortex-A), providing high energy efficiency under tight power budgets. The Ethos-N line (like the Ethos-N78) scales up to higher TOPS for mobile, automotive, and consumer electronics, deeply integrated with Arm's software toolchains (Arm NN, Vela compiler).
• Synopsys (ARC NPX Series): Synopsys provides the ARC NPX NPU IP family, optimized for heavy AI inference and embedded vision. It is heavily scalable—ranging from small configurations up to massive arrays (over 96K MACs) capable of delivering thousands of TOPS. They also offer functional safety variants (NPX6FS ) tailored for automotive (ISO 26262) and safety-critical edge applications.
• CEVA (NeuPro-M & NeuPro-Nano): CEVA is renowned for DSP and wireless IP, but their NeuPro-M and NeuPro-Nano NPU architectures are built specifically for edge AI, computer vision, and transformer models (Vision Transformers and LLM inference at the edge). NeuPro-M scales nicely up to 256 TOPS per core, while NeuPro-Nano operates as a self-contained, ultra-low-power stand-alone NPU that doesn’t strictly require a heavy host DSP or CPU.

2. Specialized & Programmable NPU/GPNPU Vendors

• Quadric (Chimera GPNPU): Quadric labels its licensable core a "General-Purpose NPU" (GPNPU). Unlike traditional fixed-function NPU accelerators that struggle or fall back to the host CPU when encountering non-standard or rapidly evolving AI operators, Quadric’s Chimera core is fully C++ programmable. It combines traditional DSP data-parallel processing with tensor-processing muscle in a single unified compiler toolchain.
• Imagination Technologies (IMG NPU): Best known for their PowerVR graphics, Imagination provides dedicated IMG NPU compute architectures designed to slot alongside their GPUs or operate independently in automotive, smart-surveillance, and mobile SoCs.

Key Considerations When Selecting NPU IP

If you share details about your target power envelope (e.g., edge vs. datacenter) and primary model types (e.g., CNNs vs. Transformers) , I can help narrow down which IP vendor best fits your performance-per-watt goals.

Yes. There is a fairly mature market for licensable NPU/AI-accelerator IP, ranging from tiny embedded inference engines to large, scalable AI accelerators.

Leading NPU IP vendors

These aren't just theoretical competitors: CEVA's latest annual report specifically identifies Arm, Cadence, Cambricon, DMP, Quadric, Imagination, NVDLA and VeriSilicon as competitors in the licensable edge-AI/NPU market.

One important distinction

I'd divide the market into three architectural categories:

• Embedded NPU: Arm Ethos-U, CEVA NeuPro-Nano, smaller VeriSilicon/Imagination configurations — optimized for low power, modest area and inference.
• Scalable edge NPU: Cadence Neo, CEVA NeuPro-M, VeriSilicon Vivante NPU, Quadric — more appropriate for automotive, cameras, robotics, consumer SoCs and multimodal AI.
• Large AI accelerator: substantially larger arrays and memory systems aimed at high-TOPS edge/server applications. These tend to involve more customization and sometimes aren't sold as a simple "drop-in NPU core."

For example, VeriSilicon describes its NPU as programmable and scalable, with configurations ranging from roughly 0.5 to 20 TOPS per convolutional kernel, with multicore configurations extending considerably higher.

What I'd shortlist for a new accelerator

If you're actually deciding which IP to license, I'd start with:

1. Cadence Neo — if you want a conventional, highly configurable NPU.
2. CEVA NeuPro-M — particularly interesting for more sophisticated edge/gen-AI workloads.
3. Arm Ethos-U — if your design is primarily Arm Cortex-based and power/area are paramount.
4. VeriSilicon Vivante NPU — worth serious consideration if you want a proven, configurable NPU with a broad SoC-IP ecosystem.
5. Quadric Chimera — especially if programmability is a differentiator rather than simply TOPS/W.

The bigger strategic question is what kind of accelerator you're designing. If you tell me your target (e.g. 10–100 TOPS edge AI, 1–10 TOPS MCU, automotive, LLM inference, vision, FPGA vs ASIC, process node, INT8/FP16/FP8, RISC-V vs Arm host), I can make a much more useful vendor-by-vendor comparison of TOPS, MAC architecture, data types, SRAM requirements, software stack, licensing model, and likely PPA.