Cadence holds a narrow lead over Synopsys for neural processing unit intellectual property cores. Synopsys is closely paired with it for automotive ISO 26262 compliant accelerator designs.
For an AI hardware accelerator, there are several established semiconductor IP vendors that license NPU cores or closely related AI accelerator IP for integration into your own ASIC or SoC. The best fit depends on whether you're building a low-power edge inference chip, an automotive processor, a vision accelerator, or a higher-throughput AI engine.
I'd start by evaluating the following vendors, separating dedicated NPU IP from programmable GPU/DSP-based AI compute and open-source designs.
1. Leading NPU IP vendors
Arm — Ethos NPU
Offers licensable NPU IP including Ethos-U55, U65 and U85, targeting efficient neural-network inference in embedded and edge devices. The U85 adds native transformer-network support, making it worth evaluating for newer AI workloads.
Best fit: embedded AI, MCU/SoC integration, low-power edge inference.
Provides scalable, configurable NPU IP, alongside Tensilica DSPs, vision processors and the NeuroEdge AI co-processor. Its AI IP platform includes software development tools for integrating and deploying neural networks.
Best fit: configurable edge AI, automotive, industrial and consumer SoCs.
Offers scalable, programmable neural-network processor IP for computer vision and AI, with configurations for different chip sizes and power budgets. Its portfolio also includes GPU and image-processing IP, which can simplify integration of a broader vision subsystem.
Best fit: vision, consumer electronics, automotive and embedded AI.
Offers dedicated deep-learning accelerator IP, including the AnDLA I350 and I370, paired with RISC-V processor IP, neural-network software tools and optimized compute libraries.
Best fit: RISC-V-based SoCs and integrated edge-AI subsystems.
Imagination Technologies — E-Series GPU with Neural Cores
Licenses programmable GPU IP with integrated matrix acceleration for AI, graphics and compute. This is an alternative to a dedicated NPU when you want one compute architecture to serve multiple workloads.
Best fit: edge AI requiring both graphics and neural-network acceleration.
A particularly relevant candidate for a new AI accelerator. NeuPro-Nano targets embedded ML, while NeuPro-M targets transformers, vision-language models and generative AI. CEVA also provides its NeuPro Studio development toolchain.
Best fit: scalable edge inference, from compact devices to higher-performance AI SoCs.
Offers licensable neuromorphic AI technology designed around event-based processing. Its approach differs from conventional dense matrix-multiplication NPUs, so it is worth investigating for workloads that can benefit from sparse, event-driven computation.
Best fit: low-power, event-driven edge AI and neuromorphic applications.
NVDLA is a configurable, open-source deep-learning inference hardware design, rather than a conventional commercial IP licensing product. It includes RTL, a software stack and development resources, and is offered under NVIDIA's Open NVDLA license, which is royalty-free subject to its terms.
Best fit: a starting point for an in-house accelerator, prototyping, or evaluating an established inference architecture.
These companies are also relevant to an NPU IP sourcing exercise, although the precise offering and licensing terms should be confirmed for your target architecture.
4. How I would shortlist them for your accelerator
The right shortlist depends heavily on the intended chip. I'd use these initial groupings:
Your design target
Vendors to evaluate first
Low-power edge inference
Arm, CEVA, Andes
Generative AI and transformer inference
CEVA, Cadence, Arm, Imagination
Computer vision and embedded SoCs
VeriSilicon, Cadence, Andes
Programmable AI compute alongside graphics
Imagination, Quadric
Neuromorphic/event-driven inference
BrainChip
Open-source RTL and architecture experimentation
NVIDIA NVDLA
These are starting points for technical evaluation, not a ranking of measured performance. Vendor claims for TOPS, power and area often use different precisions, workloads, memory assumptions and process nodes.
5. What to request from each IP vendor
Before selecting a core, request the following:
PPA data: throughput, latency, silicon area and power at your target process node.
Numeric formats: INT8, INT4, FP16, BF16 and FP8 support, as required by your models.
Memory architecture: SRAM requirements, external memory bandwidth, data reuse and DMA.
Software stack: model import, compiler, quantization, runtime, debugging and supported frameworks.
Integration and licensing: RTL availability, hard versus soft IP, supported foundries, royalties, safety certification and long-term maintenance.
One important distinction: if you are designing an accelerator for large language models or data-center inference, don't assume an edge NPU core will scale to your requirements. You may need a more specialized matrix engine, a multi-core architecture, or a custom accelerator IP engagement.
One question that would help narrow this down: What is the target market for your accelerator — edge/embedded, automotive, mobile/PC, or data-center AI? That will help identify the most relevant IP suppliers and avoid comparing architectures designed for very different power and performance envelopes.
When designing an AI hardware accelerator, several major semiconductor IP providers and specialized vendors offer licensable Neural Processing Unit (NPU) IP cores. They range from ultra-low power edge devices to high-performance data center inference engines.
Key providers of NPU and AI processor IP cores include:
Synopsys Offers the Synopsys ARC-VR / Embedded NPU and high-performance neural processor IP lines (such as ARC-NPX6 in collaboration/integration with MIPS ecosystems), delivering massive TOPS scalability and comprehensive MetaWare software toolchains.
Cadence Offers the Cadence Neo NPUs , which are highly scalable, energy-efficient, hardware-based AI engines designed to integrate easily with host processors for edge and IoT workloads.[](https://us.design-reuse.com/sip/?q=npu+ip)
Ceva Offers the Ceva-NeuPro-M family, specifically optimized for edge computing, vision transformers (ViT), and multi-modal generative AI models (like Llama architectures) with high tokens-per-second-per-watt efficiency.[](https://www.ceva-ip.com/product/ceva-neupro-m/)
Expedera Offers scalable Origin NPU IP architectures focusing on high performance-per-area and power metrics for edge and mobile generative AI.
Quadric Provides Chimera GPNPU (General Purpose Neural Processing Unit) cores, which combine traditional DSP/control processing with high-performance machine learning acceleration.[](https://us.design-reuse.com/sip/?q=npu+ip)
Openedges Technology Offers ENLIGHT Pro , an advanced, highly scalable inference NPU IP tightly integrated with memory subsystem architecture.[](https://us.design-reuse.com/sip/?q=npu+ip)
If you can share a bit more about your target application, I can help narrow this down:
Is your accelerator targeting edge/mobile (low power, <5 W) or data center/server workloads?
What data precision (e.g., INT8, FP16, BF16) and model types (CNNs, Transformers/LLMs) are you prioritizing?
Yes. If by “license NPU IP cores” you mean companies that sell/licence reusable NPU/neural-accelerator RTL/IP to semiconductor companies so they can integrate it into a custom SoC/ASIC, there is a fairly well-defined vendor market.
Edge, smartphones, automotive, data center inference
Expedera describes itself specifically as an NPU semiconductor-IP licensor; its current Origin Evolution is available for licensing and production designs.
DMP explicitly operates an IP Core License Business and lists its A3000 NPU as a licensable AI IP core.
Particularly interesting licensees / users
There are also a number of semiconductor companies that license these cores rather than developing the NPU completely in-house. Publicly documented examples include:
Microchip Technology — licensed CEVA's broad NeuPro family for incorporation across its product roadmap.
NXP Semiconductors — has used VeriSilicon's Vivante VIP NPU technology and is also a documented Arm Ethos partner.
Alif Semiconductor — early adopter of /U85 for its MCU/fusion-processor products.
One important 2026 change
If you're researching suppliers today, don't treat Synopsys ARC NPX as a separate current vendor from GlobalFoundries. GlobalFoundries acquired Synopsys' ARC Processor IP Solutions business on June 1, 2026, including ARC NPX NPU IP, and combined it with MIPS.
Also, NVDLA is worth mentioning as a different category: Nvidia's open-source NVDLA is an accelerator architecture rather than a conventional royalty-bearing commercial NPU IP vendor, so I wouldn't put it in the same licensing bucket.
For an AI accelerator project, I'd shortlist the market roughly as:Arm, CEVA, Cadence, VeriSilicon, GlobalFoundries/MIPS (ARC), Imagination, and Expedera, with DMP as a more specialized alternative. CEVA itself identifies Arm, Cadence, Imagination, VeriSilicon, Expedera, DMP and other companies as competitors in the NPU/processor-IP market.
If useful, I can next build a vendor-by-vendor comparison of these NPU IP cores—TOPS, TOPS/W, INT4/INT8/FP16/BF16, transformer/LLM support, licensing model, process nodes, safety certifications, and publicly known customers.
Alibaba T-Head Semiconductor — licensed Imagination's GPU and PowerVR NNA for its RISC-V AIoT SoCs.
Socionext, Texas Instruments and Renesas — Imagination has publicly described licensing PowerVR GPU/NNA IP to these silicon companies for automotive SoCs.
Many additional CEVA customers — CEVA's filings list semiconductor/OEM customers including Broadcom, Intel, MediaTek, Microchip, NXP, Renesas, Rockchip, Samsung, STMicroelectronics, Unisoc and others, although the public filings don't necessarily identify which particular IP each customer licensed.
